This invention relates to the testing of logic systems in semiconductor integrated circuits or chips. More specifically, the invention relates to a method and apparatus for more easily identifying common causes of logic circuit yield detractors. An alternate embodiment relates to a method and apparatus for more easily identifying common causes of integrated circuit yield detractors.
Yield is the ratio of all good chips to the total number of chips produced. It is an extremely important quantity and often determines if a program is highly profitable or a loss. A major effort in the development of a new semiconductor technology is termed “yield learning.” Yield learning covers all activities to raise yield to volume manufacturable levels. Yield detractors include process random defects, process systematic problems, mask defects or problems, and circuit marginality problems. Many of these problems have random characteristics, that is, they occur in different areas of the chip and on different circuits without any apparent pattern. This is the usual characteristic when a process is mature. As long as the defect level is sufficiently low it is acceptable. High random defect levels are a serious concern and usually indicate a more systematic problem such as contamination
Regular structures such as memory arrays and test structures built on the kerf (the space on the wafer between chips) serve as monitors for high random defect levels. There are other systematic, or repeatable, yield detractors that are more difficult to diagnose. These are problems that occur in the logic area of the chip. They may be caused by circuit marginality, mask defects, or process marginality for structures unique to logic. If these problems cause very low yield, there is a great effort undertaken to determine the cause and fix the problem. If the yield loss is low, however, or only occurs on certain lots, it may be interpreted as expected random defects. “Low” yield loss is relative to the size of the chip, the complexity of the process, and the maturity of the process. If “expected” yield is 20% and the actual yield is 16%, the difference may be attributed to random defects, when in fact it may be due to systematic defects with a common cause that may be much more easily fixed.
Chips are tested by applying a sequential set of electrical voltage levels to chip inputs and storage elements that represent logical ‘1’ and ‘0’. After the appropriate clocking signals to activate the storage elements, those storage elements and the chip outputs are sampled and compared to the expected logical value. Access to the internal storage elements may be done via a scan configuration (e.g., LSSD).
As the complexity of chips increase, there is increasing demand on the test system to store the necessary ‘1’ and ‘0’ confirmations to apply as stimulus on the inputs and expected values are the outputs to compare against. The term ‘input’ in this context means whatever elements the local stimulus is applied to, either physical chip inputs or storage elements accessible by some scan method such as LSSD.
There are two methods of reducing the storage requirements of these so-called “test patterns”. One method is to compress all the measurements sequentially into a set of storage elements known as Multiple Input Shift Register or MISR. The MISR value or signature is measured at the end of the test, which may be thousands of clock cycles or more, and compared with its expected value. Another method, known as Logic Built In Self Test or LBIST uses a structure known as a Pseudo Random Pattern Generator or PRPG, generates the stimulus in a pseudo random fashion. After the application of the pseudo random pattern and a set of functional clock cycles the results are compressed in a MISR.
In the existing state of the art, repeatable defects could be inferred if the same test patterns failed on multiple chips and especially if the same elements failed on those patterns. In a test that comprises, for example, 1,000 patterns, if test #512 fails on a number of parts, then repeatable defects are highly suspect. The existing state of the art has practical limitations. In practice, much of the chip is tested in the first few patterns so it is natural that earlier patterns will have a higher failure rate and the vast majority of these will not be common fails. If the individual outputs are counted, there is more resolution of the failure. For example, if multiple chips failed in a way that on pattern 5, output 572 as a ‘1’, then this would more definitively point to a repeatable defect as the cause of the failure.
There are still limits to the usefulness of this method, however, because there are on large chips tens or hundreds of thousands of outputs (chip outputs and latches) that are measured. It is impractical to compare all the possible failure modes for thousands of latches on thousands of patterns across thousands of chips.
Yet one more limitation of the existing method is that it is not applicable to any test that compresses measurements into a register after every cycle. This is critical, because such test methodologies, such as LBIST are increasingly used to test advanced chips.
Selective signature generation can be used to provide dynamically selectable signature generation modes that can be used to isolate and/or diagnose faults on BIST circuits. Selective signature generation can be performed as described in U.S. patent application Ser. No. 09/310,445, filed on May 12, 1999 which is incorporated herein by reference in its entirety.